-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"

-- DATE "04/30/2021 15:16:00"

-- 
-- Device: Altera EP3C40F780C8 Package FBGA780
-- 

-- 
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
-- 

LIBRARY ALTERA;
LIBRARY CYCLONEIII;
LIBRARY IEEE;
USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY 	zl_2346_5 IS
    PORT (
	en : IN std_logic;
	RA : IN std_logic_vector(1 DOWNTO 0);
	Wr : IN std_logic;
	Rd : IN std_logic;
	M : IN std_logic_vector(1 DOWNTO 0);
	rst : IN std_logic;
	clk : IN std_logic;
	datain : IN std_logic_vector(3 DOWNTO 0);
	sel : OUT std_logic_vector(2 DOWNTO 0);
	seg : OUT std_logic_vector(7 DOWNTO 0)
	);
END zl_2346_5;

-- Design Ports Information
-- sel[0]	=>  Location: PIN_AH19,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- sel[1]	=>  Location: PIN_AB16,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- sel[2]	=>  Location: PIN_AG18,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- seg[0]	=>  Location: PIN_AE16,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- seg[1]	=>  Location: PIN_AF17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- seg[2]	=>  Location: PIN_AH17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- seg[3]	=>  Location: PIN_AF16,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- seg[4]	=>  Location: PIN_AE17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- seg[5]	=>  Location: PIN_AH18,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- seg[6]	=>  Location: PIN_AG17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- seg[7]	=>  Location: PIN_N3,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- clk	=>  Location: PIN_J2,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- M[0]	=>  Location: PIN_AG21,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- M[1]	=>  Location: PIN_AC17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- rst	=>  Location: PIN_AE18,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- RA[0]	=>  Location: PIN_AD17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- RA[1]	=>  Location: PIN_AF18,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- Rd	=>  Location: PIN_AH21,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- Wr	=>  Location: PIN_Y17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- datain[0]	=>  Location: PIN_AG19,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- en	=>  Location: PIN_AH22,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- datain[1]	=>  Location: PIN_AE19,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- datain[2]	=>  Location: PIN_AG22,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- datain[3]	=>  Location: PIN_AH23,	 I/O Standard: 2.5 V,	 Current Strength: Default


ARCHITECTURE structure OF zl_2346_5 IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_en : std_logic;
SIGNAL ww_RA : std_logic_vector(1 DOWNTO 0);
SIGNAL ww_Wr : std_logic;
SIGNAL ww_Rd : std_logic;
SIGNAL ww_M : std_logic_vector(1 DOWNTO 0);
SIGNAL ww_rst : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_datain : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_sel : std_logic_vector(2 DOWNTO 0);
SIGNAL ww_seg : std_logic_vector(7 DOWNTO 0);
SIGNAL \clk~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \div_clk~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \sel[0]~output_o\ : std_logic;
SIGNAL \sel[1]~output_o\ : std_logic;
SIGNAL \sel[2]~output_o\ : std_logic;
SIGNAL \seg[0]~output_o\ : std_logic;
SIGNAL \seg[1]~output_o\ : std_logic;
SIGNAL \seg[2]~output_o\ : std_logic;
SIGNAL \seg[3]~output_o\ : std_logic;
SIGNAL \seg[4]~output_o\ : std_logic;
SIGNAL \seg[5]~output_o\ : std_logic;
SIGNAL \seg[6]~output_o\ : std_logic;
SIGNAL \seg[7]~output_o\ : std_logic;
SIGNAL \clk~input_o\ : std_logic;
SIGNAL \clk~inputclkctrl_outclk\ : std_logic;
SIGNAL \sel[0]~2_combout\ : std_logic;
SIGNAL \sel[0]~reg0_q\ : std_logic;
SIGNAL \sel[1]~0_combout\ : std_logic;
SIGNAL \sel[1]~reg0_q\ : std_logic;
SIGNAL \sel[2]~1_combout\ : std_logic;
SIGNAL \sel[2]~reg0_q\ : std_logic;
SIGNAL \count[1]~4_combout\ : std_logic;
SIGNAL \count[1]~5\ : std_logic;
SIGNAL \count[2]~6_combout\ : std_logic;
SIGNAL \count[2]~7\ : std_logic;
SIGNAL \count[3]~8_combout\ : std_logic;
SIGNAL \count[3]~9\ : std_logic;
SIGNAL \count[4]~10_combout\ : std_logic;
SIGNAL \LessThan0~0_combout\ : std_logic;
SIGNAL \div_clk~0_combout\ : std_logic;
SIGNAL \div_clk~feeder_combout\ : std_logic;
SIGNAL \div_clk~q\ : std_logic;
SIGNAL \div_clk~clkctrl_outclk\ : std_logic;
SIGNAL \M[1]~input_o\ : std_logic;
SIGNAL \M[0]~input_o\ : std_logic;
SIGNAL \datain[2]~input_o\ : std_logic;
SIGNAL \D[2]~feeder_combout\ : std_logic;
SIGNAL \en~input_o\ : std_logic;
SIGNAL \datain[1]~input_o\ : std_logic;
SIGNAL \D[1]~feeder_combout\ : std_logic;
SIGNAL \Add1~0_combout\ : std_logic;
SIGNAL \datain[0]~input_o\ : std_logic;
SIGNAL \D[0]~feeder_combout\ : std_logic;
SIGNAL \Mux15~0_combout\ : std_logic;
SIGNAL \rst~input_o\ : std_logic;
SIGNAL \PC[3]~0_combout\ : std_logic;
SIGNAL \Add1~1\ : std_logic;
SIGNAL \Add1~2_combout\ : std_logic;
SIGNAL \Mux14~0_combout\ : std_logic;
SIGNAL \Add1~3\ : std_logic;
SIGNAL \Add1~4_combout\ : std_logic;
SIGNAL \Mux13~0_combout\ : std_logic;
SIGNAL \Add1~5\ : std_logic;
SIGNAL \Add1~6_combout\ : std_logic;
SIGNAL \datain[3]~input_o\ : std_logic;
SIGNAL \D[3]~feeder_combout\ : std_logic;
SIGNAL \Mux12~0_combout\ : std_logic;
SIGNAL \Add1~7\ : std_logic;
SIGNAL \Add1~8_combout\ : std_logic;
SIGNAL \D[4]~feeder_combout\ : std_logic;
SIGNAL \Mux11~0_combout\ : std_logic;
SIGNAL \R3[0]~feeder_combout\ : std_logic;
SIGNAL \RA[0]~input_o\ : std_logic;
SIGNAL \Rd~input_o\ : std_logic;
SIGNAL \RA[1]~input_o\ : std_logic;
SIGNAL \Wr~input_o\ : std_logic;
SIGNAL \Decoder0~3_combout\ : std_logic;
SIGNAL \R1[0]~feeder_combout\ : std_logic;
SIGNAL \Decoder0~0_combout\ : std_logic;
SIGNAL \Decoder0~2_combout\ : std_logic;
SIGNAL \R2[0]~feeder_combout\ : std_logic;
SIGNAL \Decoder0~1_combout\ : std_logic;
SIGNAL \Mux7~0_combout\ : std_logic;
SIGNAL \Mux7~1_combout\ : std_logic;
SIGNAL \Q[7]~0_combout\ : std_logic;
SIGNAL \R3[4]~feeder_combout\ : std_logic;
SIGNAL \R2[4]~feeder_combout\ : std_logic;
SIGNAL \R1[4]~feeder_combout\ : std_logic;
SIGNAL \Mux3~0_combout\ : std_logic;
SIGNAL \Mux3~1_combout\ : std_logic;
SIGNAL \Mux19~0_combout\ : std_logic;
SIGNAL \Mux19~1_combout\ : std_logic;
SIGNAL \Mux19~2_combout\ : std_logic;
SIGNAL \R3[1]~feeder_combout\ : std_logic;
SIGNAL \R2[1]~feeder_combout\ : std_logic;
SIGNAL \Mux6~0_combout\ : std_logic;
SIGNAL \Mux6~1_combout\ : std_logic;
SIGNAL \Add1~9\ : std_logic;
SIGNAL \Add1~10_combout\ : std_logic;
SIGNAL \Mux10~0_combout\ : std_logic;
SIGNAL \Mux18~0_combout\ : std_logic;
SIGNAL \R3[5]~feeder_combout\ : std_logic;
SIGNAL \R2[5]~feeder_combout\ : std_logic;
SIGNAL \R1[5]~feeder_combout\ : std_logic;
SIGNAL \Mux2~0_combout\ : std_logic;
SIGNAL \Mux2~1_combout\ : std_logic;
SIGNAL \Mux18~1_combout\ : std_logic;
SIGNAL \Mux18~2_combout\ : std_logic;
SIGNAL \R1[2]~feeder_combout\ : std_logic;
SIGNAL \R3[2]~feeder_combout\ : std_logic;
SIGNAL \R2[2]~feeder_combout\ : std_logic;
SIGNAL \Mux5~0_combout\ : std_logic;
SIGNAL \Mux5~1_combout\ : std_logic;
SIGNAL \D[6]~feeder_combout\ : std_logic;
SIGNAL \R2[6]~feeder_combout\ : std_logic;
SIGNAL \R3[6]~feeder_combout\ : std_logic;
SIGNAL \R1[6]~feeder_combout\ : std_logic;
SIGNAL \Mux1~0_combout\ : std_logic;
SIGNAL \Mux1~1_combout\ : std_logic;
SIGNAL \Mux17~0_combout\ : std_logic;
SIGNAL \Add1~11\ : std_logic;
SIGNAL \Add1~12_combout\ : std_logic;
SIGNAL \Mux9~0_combout\ : std_logic;
SIGNAL \Mux17~1_combout\ : std_logic;
SIGNAL \Mux17~2_combout\ : std_logic;
SIGNAL \Add1~13\ : std_logic;
SIGNAL \Add1~14_combout\ : std_logic;
SIGNAL \Mux8~0_combout\ : std_logic;
SIGNAL \R2[7]~feeder_combout\ : std_logic;
SIGNAL \R3[7]~feeder_combout\ : std_logic;
SIGNAL \R1[7]~feeder_combout\ : std_logic;
SIGNAL \Mux0~0_combout\ : std_logic;
SIGNAL \Mux0~1_combout\ : std_logic;
SIGNAL \R3[3]~feeder_combout\ : std_logic;
SIGNAL \R1[3]~feeder_combout\ : std_logic;
SIGNAL \R2[3]~feeder_combout\ : std_logic;
SIGNAL \Mux4~0_combout\ : std_logic;
SIGNAL \Mux4~1_combout\ : std_logic;
SIGNAL \Mux16~0_combout\ : std_logic;
SIGNAL \Mux16~1_combout\ : std_logic;
SIGNAL \Mux16~2_combout\ : std_logic;
SIGNAL \WideOr6~0_combout\ : std_logic;
SIGNAL \seg[0]~reg0_q\ : std_logic;
SIGNAL \WideOr5~0_combout\ : std_logic;
SIGNAL \seg[1]~reg0_q\ : std_logic;
SIGNAL \WideOr4~0_combout\ : std_logic;
SIGNAL \seg[2]~reg0_q\ : std_logic;
SIGNAL \WideOr3~0_combout\ : std_logic;
SIGNAL \seg[3]~reg0_q\ : std_logic;
SIGNAL \WideOr2~0_combout\ : std_logic;
SIGNAL \seg[4]~reg0_q\ : std_logic;
SIGNAL \WideOr1~0_combout\ : std_logic;
SIGNAL \seg[5]~reg0_q\ : std_logic;
SIGNAL \WideOr0~0_combout\ : std_logic;
SIGNAL \seg[6]~reg0_q\ : std_logic;
SIGNAL data : std_logic_vector(3 DOWNTO 0);
SIGNAL count : std_logic_vector(4 DOWNTO 0);
SIGNAL R3 : std_logic_vector(7 DOWNTO 0);
SIGNAL R2 : std_logic_vector(7 DOWNTO 0);
SIGNAL R1 : std_logic_vector(7 DOWNTO 0);
SIGNAL R0 : std_logic_vector(7 DOWNTO 0);
SIGNAL Q : std_logic_vector(7 DOWNTO 0);
SIGNAL PC : std_logic_vector(7 DOWNTO 0);
SIGNAL D : std_logic_vector(7 DOWNTO 0);
SIGNAL \ALT_INV_en~input_o\ : std_logic;

BEGIN

ww_en <= en;
ww_RA <= RA;
ww_Wr <= Wr;
ww_Rd <= Rd;
ww_M <= M;
ww_rst <= rst;
ww_clk <= clk;
ww_datain <= datain;
sel <= ww_sel;
seg <= ww_seg;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

\clk~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \clk~input_o\);

\div_clk~clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \div_clk~q\);
\ALT_INV_en~input_o\ <= NOT \en~input_o\;

-- Location: IOOBUF_X45_Y0_N16
\sel[0]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \sel[0]~reg0_q\,
	devoe => ww_devoe,
	o => \sel[0]~output_o\);

-- Location: IOOBUF_X43_Y0_N16
\sel[1]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \sel[1]~reg0_q\,
	devoe => ww_devoe,
	o => \sel[1]~output_o\);

-- Location: IOOBUF_X45_Y0_N30
\sel[2]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \sel[2]~reg0_q\,
	devoe => ww_devoe,
	o => \sel[2]~output_o\);

-- Location: IOOBUF_X43_Y0_N9
\seg[0]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \seg[0]~reg0_q\,
	devoe => ww_devoe,
	o => \seg[0]~output_o\);

-- Location: IOOBUF_X43_Y0_N23
\seg[1]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \seg[1]~reg0_q\,
	devoe => ww_devoe,
	o => \seg[1]~output_o\);

-- Location: IOOBUF_X41_Y0_N9
\seg[2]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \seg[2]~reg0_q\,
	devoe => ww_devoe,
	o => \seg[2]~output_o\);

-- Location: IOOBUF_X43_Y0_N30
\seg[3]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \seg[3]~reg0_q\,
	devoe => ww_devoe,
	o => \seg[3]~output_o\);

-- Location: IOOBUF_X43_Y0_N2
\seg[4]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \seg[4]~reg0_q\,
	devoe => ww_devoe,
	o => \seg[4]~output_o\);

-- Location: IOOBUF_X45_Y0_N23
\seg[5]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \seg[5]~reg0_q\,
	devoe => ww_devoe,
	o => \seg[5]~output_o\);

-- Location: IOOBUF_X41_Y0_N16
\seg[6]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \seg[6]~reg0_q\,
	devoe => ww_devoe,
	o => \seg[6]~output_o\);

-- Location: IOOBUF_X0_Y29_N2
\seg[7]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \seg[7]~output_o\);

-- Location: IOIBUF_X0_Y21_N1
\clk~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_clk,
	o => \clk~input_o\);

-- Location: CLKCTRL_G4
\clk~inputclkctrl\ : cycloneiii_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \clk~inputclkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \clk~inputclkctrl_outclk\);

-- Location: LCCOMB_X44_Y3_N6
\sel[0]~2\ : cycloneiii_lcell_comb
-- Equation(s):
-- \sel[0]~2_combout\ = !\sel[0]~reg0_q\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \sel[0]~reg0_q\,
	combout => \sel[0]~2_combout\);

-- Location: FF_X44_Y3_N7
\sel[0]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \sel[0]~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \sel[0]~reg0_q\);

-- Location: LCCOMB_X44_Y3_N28
\sel[1]~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \sel[1]~0_combout\ = \sel[1]~reg0_q\ $ (\sel[0]~reg0_q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \sel[1]~reg0_q\,
	datad => \sel[0]~reg0_q\,
	combout => \sel[1]~0_combout\);

-- Location: FF_X44_Y3_N29
\sel[1]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \sel[1]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \sel[1]~reg0_q\);

-- Location: LCCOMB_X44_Y3_N0
\sel[2]~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \sel[2]~1_combout\ = \sel[2]~reg0_q\ $ (((\sel[1]~reg0_q\ & \sel[0]~reg0_q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \sel[1]~reg0_q\,
	datac => \sel[2]~reg0_q\,
	datad => \sel[0]~reg0_q\,
	combout => \sel[2]~1_combout\);

-- Location: FF_X44_Y3_N1
\sel[2]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \sel[2]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \sel[2]~reg0_q\);

-- Location: LCCOMB_X44_Y3_N16
\count[1]~4\ : cycloneiii_lcell_comb
-- Equation(s):
-- \count[1]~4_combout\ = (\sel[0]~reg0_q\ & (count(1) $ (VCC))) # (!\sel[0]~reg0_q\ & (count(1) & VCC))
-- \count[1]~5\ = CARRY((\sel[0]~reg0_q\ & count(1)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0110011010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \sel[0]~reg0_q\,
	datab => count(1),
	datad => VCC,
	combout => \count[1]~4_combout\,
	cout => \count[1]~5\);

-- Location: FF_X44_Y3_N17
\count[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \count[1]~4_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => count(1));

-- Location: LCCOMB_X44_Y3_N18
\count[2]~6\ : cycloneiii_lcell_comb
-- Equation(s):
-- \count[2]~6_combout\ = (count(2) & (!\count[1]~5\)) # (!count(2) & ((\count[1]~5\) # (GND)))
-- \count[2]~7\ = CARRY((!\count[1]~5\) # (!count(2)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => count(2),
	datad => VCC,
	cin => \count[1]~5\,
	combout => \count[2]~6_combout\,
	cout => \count[2]~7\);

-- Location: FF_X44_Y3_N19
\count[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \count[2]~6_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => count(2));

-- Location: LCCOMB_X44_Y3_N20
\count[3]~8\ : cycloneiii_lcell_comb
-- Equation(s):
-- \count[3]~8_combout\ = (count(3) & (\count[2]~7\ $ (GND))) # (!count(3) & (!\count[2]~7\ & VCC))
-- \count[3]~9\ = CARRY((count(3) & !\count[2]~7\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => count(3),
	datad => VCC,
	cin => \count[2]~7\,
	combout => \count[3]~8_combout\,
	cout => \count[3]~9\);

-- Location: FF_X44_Y3_N21
\count[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \count[3]~8_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => count(3));

-- Location: LCCOMB_X44_Y3_N22
\count[4]~10\ : cycloneiii_lcell_comb
-- Equation(s):
-- \count[4]~10_combout\ = count(4) $ (\count[3]~9\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011010",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => count(4),
	cin => \count[3]~9\,
	combout => \count[4]~10_combout\);

-- Location: FF_X44_Y3_N23
\count[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \count[4]~10_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => count(4));

-- Location: LCCOMB_X44_Y3_N24
\LessThan0~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \LessThan0~0_combout\ = (((!count(2)) # (!count(3))) # (!count(1))) # (!\sel[0]~reg0_q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \sel[0]~reg0_q\,
	datab => count(1),
	datac => count(3),
	datad => count(2),
	combout => \LessThan0~0_combout\);

-- Location: LCCOMB_X44_Y3_N8
\div_clk~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \div_clk~0_combout\ = \div_clk~q\ $ (((count(4) & !\LessThan0~0_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101001011010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \div_clk~q\,
	datac => count(4),
	datad => \LessThan0~0_combout\,
	combout => \div_clk~0_combout\);

-- Location: LCCOMB_X44_Y3_N30
\div_clk~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \div_clk~feeder_combout\ = \div_clk~0_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \div_clk~0_combout\,
	combout => \div_clk~feeder_combout\);

-- Location: FF_X44_Y3_N31
div_clk : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div_clk~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div_clk~q\);

-- Location: CLKCTRL_G15
\div_clk~clkctrl\ : cycloneiii_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \div_clk~clkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \div_clk~clkctrl_outclk\);

-- Location: IOIBUF_X48_Y0_N8
\M[1]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_M(1),
	o => \M[1]~input_o\);

-- Location: IOIBUF_X48_Y0_N15
\M[0]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_M(0),
	o => \M[0]~input_o\);

-- Location: IOIBUF_X50_Y0_N29
\datain[2]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_datain(2),
	o => \datain[2]~input_o\);

-- Location: LCCOMB_X51_Y3_N24
\D[2]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \D[2]~feeder_combout\ = \datain[2]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \datain[2]~input_o\,
	combout => \D[2]~feeder_combout\);

-- Location: IOIBUF_X50_Y0_N22
\en~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_en,
	o => \en~input_o\);

-- Location: FF_X51_Y3_N25
\D[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \D[2]~feeder_combout\,
	ena => \ALT_INV_en~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => D(2));

-- Location: IOIBUF_X50_Y0_N1
\datain[1]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_datain(1),
	o => \datain[1]~input_o\);

-- Location: LCCOMB_X51_Y3_N0
\D[1]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \D[1]~feeder_combout\ = \datain[1]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \datain[1]~input_o\,
	combout => \D[1]~feeder_combout\);

-- Location: FF_X51_Y3_N1
\D[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \D[1]~feeder_combout\,
	ena => \ALT_INV_en~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => D(1));

-- Location: LCCOMB_X46_Y3_N12
\Add1~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add1~0_combout\ = PC(0) $ (VCC)
-- \Add1~1\ = CARRY(PC(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101010110101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => PC(0),
	datad => VCC,
	combout => \Add1~0_combout\,
	cout => \Add1~1\);

-- Location: IOIBUF_X50_Y0_N15
\datain[0]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_datain(0),
	o => \datain[0]~input_o\);

-- Location: LCCOMB_X51_Y3_N22
\D[0]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \D[0]~feeder_combout\ = \datain[0]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \datain[0]~input_o\,
	combout => \D[0]~feeder_combout\);

-- Location: FF_X51_Y3_N23
\D[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \D[0]~feeder_combout\,
	ena => \ALT_INV_en~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => D(0));

-- Location: LCCOMB_X46_Y3_N30
\Mux15~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux15~0_combout\ = (\M[1]~input_o\ & (!\M[0]~input_o\ & (\Add1~0_combout\))) # (!\M[1]~input_o\ & ((\M[0]~input_o\ & (\Add1~0_combout\)) # (!\M[0]~input_o\ & ((D(0))))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111000101100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \M[1]~input_o\,
	datab => \M[0]~input_o\,
	datac => \Add1~0_combout\,
	datad => D(0),
	combout => \Mux15~0_combout\);

-- Location: IOIBUF_X48_Y0_N29
\rst~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_rst,
	o => \rst~input_o\);

-- Location: LCCOMB_X48_Y3_N4
\PC[3]~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \PC[3]~0_combout\ = ((!\rst~input_o\) # (!\M[1]~input_o\)) # (!\M[0]~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101111111111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \M[0]~input_o\,
	datac => \M[1]~input_o\,
	datad => \rst~input_o\,
	combout => \PC[3]~0_combout\);

-- Location: FF_X46_Y3_N31
\PC[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \Mux15~0_combout\,
	ena => \PC[3]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => PC(0));

-- Location: LCCOMB_X46_Y3_N14
\Add1~2\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add1~2_combout\ = (\M[0]~input_o\ & ((PC(1) & (!\Add1~1\)) # (!PC(1) & ((\Add1~1\) # (GND))))) # (!\M[0]~input_o\ & ((PC(1) & (\Add1~1\ & VCC)) # (!PC(1) & (!\Add1~1\))))
-- \Add1~3\ = CARRY((\M[0]~input_o\ & ((!\Add1~1\) # (!PC(1)))) # (!\M[0]~input_o\ & (!PC(1) & !\Add1~1\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0110100100101011",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \M[0]~input_o\,
	datab => PC(1),
	datad => VCC,
	cin => \Add1~1\,
	combout => \Add1~2_combout\,
	cout => \Add1~3\);

-- Location: LCCOMB_X46_Y3_N2
\Mux14~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux14~0_combout\ = (\M[1]~input_o\ & (((\Add1~2_combout\ & !\M[0]~input_o\)))) # (!\M[1]~input_o\ & ((\M[0]~input_o\ & ((\Add1~2_combout\))) # (!\M[0]~input_o\ & (D(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011000011100010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => D(1),
	datab => \M[1]~input_o\,
	datac => \Add1~2_combout\,
	datad => \M[0]~input_o\,
	combout => \Mux14~0_combout\);

-- Location: FF_X46_Y3_N3
\PC[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \Mux14~0_combout\,
	ena => \PC[3]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => PC(1));

-- Location: LCCOMB_X46_Y3_N16
\Add1~4\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add1~4_combout\ = ((\M[0]~input_o\ $ (PC(2) $ (\Add1~3\)))) # (GND)
-- \Add1~5\ = CARRY((\M[0]~input_o\ & (PC(2) & !\Add1~3\)) # (!\M[0]~input_o\ & ((PC(2)) # (!\Add1~3\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1001011001001101",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \M[0]~input_o\,
	datab => PC(2),
	datad => VCC,
	cin => \Add1~3\,
	combout => \Add1~4_combout\,
	cout => \Add1~5\);

-- Location: LCCOMB_X46_Y3_N6
\Mux13~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux13~0_combout\ = (\M[1]~input_o\ & (((!\M[0]~input_o\ & \Add1~4_combout\)))) # (!\M[1]~input_o\ & ((\M[0]~input_o\ & ((\Add1~4_combout\))) # (!\M[0]~input_o\ & (D(2)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011111000000010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => D(2),
	datab => \M[1]~input_o\,
	datac => \M[0]~input_o\,
	datad => \Add1~4_combout\,
	combout => \Mux13~0_combout\);

-- Location: FF_X46_Y3_N7
\PC[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \Mux13~0_combout\,
	ena => \PC[3]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => PC(2));

-- Location: LCCOMB_X46_Y3_N18
\Add1~6\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add1~6_combout\ = (PC(3) & ((\M[0]~input_o\ & (!\Add1~5\)) # (!\M[0]~input_o\ & (\Add1~5\ & VCC)))) # (!PC(3) & ((\M[0]~input_o\ & ((\Add1~5\) # (GND))) # (!\M[0]~input_o\ & (!\Add1~5\))))
-- \Add1~7\ = CARRY((PC(3) & (\M[0]~input_o\ & !\Add1~5\)) # (!PC(3) & ((\M[0]~input_o\) # (!\Add1~5\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0110100101001101",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => PC(3),
	datab => \M[0]~input_o\,
	datad => VCC,
	cin => \Add1~5\,
	combout => \Add1~6_combout\,
	cout => \Add1~7\);

-- Location: IOIBUF_X50_Y0_N8
\datain[3]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_datain(3),
	o => \datain[3]~input_o\);

-- Location: LCCOMB_X51_Y3_N4
\D[3]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \D[3]~feeder_combout\ = \datain[3]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \datain[3]~input_o\,
	combout => \D[3]~feeder_combout\);

-- Location: FF_X51_Y3_N5
\D[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \D[3]~feeder_combout\,
	ena => \ALT_INV_en~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => D(3));

-- Location: LCCOMB_X46_Y3_N10
\Mux12~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux12~0_combout\ = (\M[1]~input_o\ & (\Add1~6_combout\ & (!\M[0]~input_o\))) # (!\M[1]~input_o\ & ((\M[0]~input_o\ & (\Add1~6_combout\)) # (!\M[0]~input_o\ & ((D(3))))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100110101001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \M[1]~input_o\,
	datab => \Add1~6_combout\,
	datac => \M[0]~input_o\,
	datad => D(3),
	combout => \Mux12~0_combout\);

-- Location: FF_X46_Y3_N11
\PC[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \Mux12~0_combout\,
	ena => \PC[3]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => PC(3));

-- Location: LCCOMB_X46_Y3_N20
\Add1~8\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add1~8_combout\ = ((\M[0]~input_o\ $ (PC(4) $ (\Add1~7\)))) # (GND)
-- \Add1~9\ = CARRY((\M[0]~input_o\ & (PC(4) & !\Add1~7\)) # (!\M[0]~input_o\ & ((PC(4)) # (!\Add1~7\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1001011001001101",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \M[0]~input_o\,
	datab => PC(4),
	datad => VCC,
	cin => \Add1~7\,
	combout => \Add1~8_combout\,
	cout => \Add1~9\);

-- Location: LCCOMB_X49_Y3_N20
\D[4]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \D[4]~feeder_combout\ = \datain[0]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \datain[0]~input_o\,
	combout => \D[4]~feeder_combout\);

-- Location: FF_X49_Y3_N21
\D[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \D[4]~feeder_combout\,
	ena => \en~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => D(4));

-- Location: LCCOMB_X46_Y3_N8
\Mux11~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux11~0_combout\ = (\M[1]~input_o\ & (\Add1~8_combout\ & (!\M[0]~input_o\))) # (!\M[1]~input_o\ & ((\M[0]~input_o\ & (\Add1~8_combout\)) # (!\M[0]~input_o\ & ((D(4))))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100110101001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \M[1]~input_o\,
	datab => \Add1~8_combout\,
	datac => \M[0]~input_o\,
	datad => D(4),
	combout => \Mux11~0_combout\);

-- Location: FF_X46_Y3_N9
\PC[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \Mux11~0_combout\,
	ena => \PC[3]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => PC(4));

-- Location: LCCOMB_X50_Y3_N8
\R3[0]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \R3[0]~feeder_combout\ = D(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => D(0),
	combout => \R3[0]~feeder_combout\);

-- Location: IOIBUF_X45_Y0_N8
\RA[0]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_RA(0),
	o => \RA[0]~input_o\);

-- Location: IOIBUF_X48_Y0_N1
\Rd~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_Rd,
	o => \Rd~input_o\);

-- Location: IOIBUF_X45_Y0_N1
\RA[1]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_RA(1),
	o => \RA[1]~input_o\);

-- Location: IOIBUF_X48_Y0_N22
\Wr~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_Wr,
	o => \Wr~input_o\);

-- Location: LCCOMB_X48_Y3_N12
\Decoder0~3\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Decoder0~3_combout\ = (\RA[0]~input_o\ & (\Rd~input_o\ & (\RA[1]~input_o\ & !\Wr~input_o\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000010000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \RA[0]~input_o\,
	datab => \Rd~input_o\,
	datac => \RA[1]~input_o\,
	datad => \Wr~input_o\,
	combout => \Decoder0~3_combout\);

-- Location: FF_X50_Y3_N9
\R3[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \R3[0]~feeder_combout\,
	ena => \Decoder0~3_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R3(0));

-- Location: LCCOMB_X51_Y3_N20
\R1[0]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \R1[0]~feeder_combout\ = D(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => D(0),
	combout => \R1[0]~feeder_combout\);

-- Location: LCCOMB_X48_Y3_N22
\Decoder0~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Decoder0~0_combout\ = (\RA[0]~input_o\ & (\Rd~input_o\ & (!\RA[1]~input_o\ & !\Wr~input_o\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \RA[0]~input_o\,
	datab => \Rd~input_o\,
	datac => \RA[1]~input_o\,
	datad => \Wr~input_o\,
	combout => \Decoder0~0_combout\);

-- Location: FF_X51_Y3_N21
\R1[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \R1[0]~feeder_combout\,
	ena => \Decoder0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R1(0));

-- Location: LCCOMB_X48_Y3_N30
\Decoder0~2\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Decoder0~2_combout\ = (!\RA[0]~input_o\ & (\Rd~input_o\ & (!\RA[1]~input_o\ & !\Wr~input_o\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \RA[0]~input_o\,
	datab => \Rd~input_o\,
	datac => \RA[1]~input_o\,
	datad => \Wr~input_o\,
	combout => \Decoder0~2_combout\);

-- Location: FF_X48_Y3_N27
\R0[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	asdata => D(0),
	sload => VCC,
	ena => \Decoder0~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R0(0));

-- Location: LCCOMB_X49_Y3_N6
\R2[0]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \R2[0]~feeder_combout\ = D(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => D(0),
	combout => \R2[0]~feeder_combout\);

-- Location: LCCOMB_X48_Y3_N20
\Decoder0~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Decoder0~1_combout\ = (!\RA[0]~input_o\ & (\Rd~input_o\ & (\RA[1]~input_o\ & !\Wr~input_o\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000001000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \RA[0]~input_o\,
	datab => \Rd~input_o\,
	datac => \RA[1]~input_o\,
	datad => \Wr~input_o\,
	combout => \Decoder0~1_combout\);

-- Location: FF_X49_Y3_N7
\R2[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \R2[0]~feeder_combout\,
	ena => \Decoder0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R2(0));

-- Location: LCCOMB_X48_Y3_N26
\Mux7~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux7~0_combout\ = (\RA[0]~input_o\ & (\RA[1]~input_o\)) # (!\RA[0]~input_o\ & ((\RA[1]~input_o\ & ((R2(0)))) # (!\RA[1]~input_o\ & (R0(0)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101110010011000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \RA[0]~input_o\,
	datab => \RA[1]~input_o\,
	datac => R0(0),
	datad => R2(0),
	combout => \Mux7~0_combout\);

-- Location: LCCOMB_X45_Y3_N4
\Mux7~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux7~1_combout\ = (\RA[0]~input_o\ & ((\Mux7~0_combout\ & (R3(0))) # (!\Mux7~0_combout\ & ((R1(0)))))) # (!\RA[0]~input_o\ & (((\Mux7~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101111000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => R3(0),
	datab => \RA[0]~input_o\,
	datac => R1(0),
	datad => \Mux7~0_combout\,
	combout => \Mux7~1_combout\);

-- Location: LCCOMB_X48_Y3_N16
\Q[7]~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Q[7]~0_combout\ = (!\Rd~input_o\ & \Wr~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \Rd~input_o\,
	datad => \Wr~input_o\,
	combout => \Q[7]~0_combout\);

-- Location: FF_X45_Y3_N5
\Q[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \Mux7~1_combout\,
	ena => \Q[7]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => Q(0));

-- Location: LCCOMB_X50_Y3_N10
\R3[4]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \R3[4]~feeder_combout\ = D(4)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => D(4),
	combout => \R3[4]~feeder_combout\);

-- Location: FF_X50_Y3_N11
\R3[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \R3[4]~feeder_combout\,
	ena => \Decoder0~3_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R3(4));

-- Location: LCCOMB_X49_Y3_N28
\R2[4]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \R2[4]~feeder_combout\ = D(4)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => D(4),
	combout => \R2[4]~feeder_combout\);

-- Location: FF_X49_Y3_N29
\R2[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \R2[4]~feeder_combout\,
	ena => \Decoder0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R2(4));

-- Location: FF_X48_Y3_N29
\R0[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	asdata => D(4),
	sload => VCC,
	ena => \Decoder0~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R0(4));

-- Location: LCCOMB_X48_Y3_N2
\R1[4]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \R1[4]~feeder_combout\ = D(4)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => D(4),
	combout => \R1[4]~feeder_combout\);

-- Location: FF_X48_Y3_N3
\R1[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \R1[4]~feeder_combout\,
	ena => \Decoder0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R1(4));

-- Location: LCCOMB_X48_Y3_N28
\Mux3~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux3~0_combout\ = (\RA[0]~input_o\ & ((\RA[1]~input_o\) # ((R1(4))))) # (!\RA[0]~input_o\ & (!\RA[1]~input_o\ & (R0(4))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101010011000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \RA[0]~input_o\,
	datab => \RA[1]~input_o\,
	datac => R0(4),
	datad => R1(4),
	combout => \Mux3~0_combout\);

-- Location: LCCOMB_X45_Y3_N10
\Mux3~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux3~1_combout\ = (\RA[1]~input_o\ & ((\Mux3~0_combout\ & (R3(4))) # (!\Mux3~0_combout\ & ((R2(4)))))) # (!\RA[1]~input_o\ & (((\Mux3~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101110110100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \RA[1]~input_o\,
	datab => R3(4),
	datac => R2(4),
	datad => \Mux3~0_combout\,
	combout => \Mux3~1_combout\);

-- Location: FF_X45_Y3_N11
\Q[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \Mux3~1_combout\,
	ena => \Q[7]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => Q(4));

-- Location: LCCOMB_X45_Y3_N16
\Mux19~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux19~0_combout\ = (\sel[2]~reg0_q\ & (\sel[0]~reg0_q\)) # (!\sel[2]~reg0_q\ & ((\sel[0]~reg0_q\ & (Q(0))) # (!\sel[0]~reg0_q\ & ((Q(4))))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101100111001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \sel[2]~reg0_q\,
	datab => \sel[0]~reg0_q\,
	datac => Q(0),
	datad => Q(4),
	combout => \Mux19~0_combout\);

-- Location: LCCOMB_X45_Y3_N2
\Mux19~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux19~1_combout\ = (\sel[2]~reg0_q\ & ((\Mux19~0_combout\ & ((PC(0)))) # (!\Mux19~0_combout\ & (PC(4))))) # (!\sel[2]~reg0_q\ & (((\Mux19~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111010110001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \sel[2]~reg0_q\,
	datab => PC(4),
	datac => PC(0),
	datad => \Mux19~0_combout\,
	combout => \Mux19~1_combout\);

-- Location: LCCOMB_X45_Y3_N22
\Mux19~2\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux19~2_combout\ = (!\sel[1]~reg0_q\ & \Mux19~1_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \sel[1]~reg0_q\,
	datad => \Mux19~1_combout\,
	combout => \Mux19~2_combout\);

-- Location: FF_X45_Y3_N23
\data[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Mux19~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => data(0));

-- Location: FF_X46_Y3_N21
\R1[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	asdata => D(1),
	sload => VCC,
	ena => \Decoder0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R1(1));

-- Location: LCCOMB_X50_Y3_N28
\R3[1]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \R3[1]~feeder_combout\ = D(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => D(1),
	combout => \R3[1]~feeder_combout\);

-- Location: FF_X50_Y3_N29
\R3[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \R3[1]~feeder_combout\,
	ena => \Decoder0~3_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R3(1));

-- Location: FF_X52_Y3_N7
\R0[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	asdata => D(1),
	sload => VCC,
	ena => \Decoder0~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R0(1));

-- Location: LCCOMB_X52_Y3_N0
\R2[1]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \R2[1]~feeder_combout\ = D(1)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => D(1),
	combout => \R2[1]~feeder_combout\);

-- Location: FF_X52_Y3_N1
\R2[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \R2[1]~feeder_combout\,
	ena => \Decoder0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R2(1));

-- Location: LCCOMB_X52_Y3_N6
\Mux6~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux6~0_combout\ = (\RA[0]~input_o\ & (\RA[1]~input_o\)) # (!\RA[0]~input_o\ & ((\RA[1]~input_o\ & ((R2(1)))) # (!\RA[1]~input_o\ & (R0(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101110010011000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \RA[0]~input_o\,
	datab => \RA[1]~input_o\,
	datac => R0(1),
	datad => R2(1),
	combout => \Mux6~0_combout\);

-- Location: LCCOMB_X45_Y3_N0
\Mux6~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux6~1_combout\ = (\RA[0]~input_o\ & ((\Mux6~0_combout\ & ((R3(1)))) # (!\Mux6~0_combout\ & (R1(1))))) # (!\RA[0]~input_o\ & (((\Mux6~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111001110001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => R1(1),
	datab => \RA[0]~input_o\,
	datac => R3(1),
	datad => \Mux6~0_combout\,
	combout => \Mux6~1_combout\);

-- Location: FF_X45_Y3_N1
\Q[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \Mux6~1_combout\,
	ena => \Q[7]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => Q(1));

-- Location: LCCOMB_X46_Y3_N22
\Add1~10\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add1~10_combout\ = (PC(5) & ((\M[0]~input_o\ & (!\Add1~9\)) # (!\M[0]~input_o\ & (\Add1~9\ & VCC)))) # (!PC(5) & ((\M[0]~input_o\ & ((\Add1~9\) # (GND))) # (!\M[0]~input_o\ & (!\Add1~9\))))
-- \Add1~11\ = CARRY((PC(5) & (\M[0]~input_o\ & !\Add1~9\)) # (!PC(5) & ((\M[0]~input_o\) # (!\Add1~9\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0110100101001101",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => PC(5),
	datab => \M[0]~input_o\,
	datad => VCC,
	cin => \Add1~9\,
	combout => \Add1~10_combout\,
	cout => \Add1~11\);

-- Location: FF_X49_Y3_N11
\D[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \datain[1]~input_o\,
	sload => VCC,
	ena => \en~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => D(5));

-- Location: LCCOMB_X46_Y3_N4
\Mux10~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux10~0_combout\ = (\M[1]~input_o\ & (!\M[0]~input_o\ & (\Add1~10_combout\))) # (!\M[1]~input_o\ & ((\M[0]~input_o\ & (\Add1~10_combout\)) # (!\M[0]~input_o\ & ((D(5))))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111000101100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \M[1]~input_o\,
	datab => \M[0]~input_o\,
	datac => \Add1~10_combout\,
	datad => D(5),
	combout => \Mux10~0_combout\);

-- Location: FF_X46_Y3_N5
\PC[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \Mux10~0_combout\,
	ena => \PC[3]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => PC(5));

-- Location: LCCOMB_X45_Y3_N26
\Mux18~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux18~0_combout\ = (\sel[2]~reg0_q\ & (((\sel[0]~reg0_q\) # (PC(5))))) # (!\sel[2]~reg0_q\ & ((Q(1)) # ((!\sel[0]~reg0_q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110111111100101",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \sel[2]~reg0_q\,
	datab => Q(1),
	datac => \sel[0]~reg0_q\,
	datad => PC(5),
	combout => \Mux18~0_combout\);

-- Location: LCCOMB_X50_Y3_N2
\R3[5]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \R3[5]~feeder_combout\ = D(5)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => D(5),
	combout => \R3[5]~feeder_combout\);

-- Location: FF_X50_Y3_N3
\R3[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \R3[5]~feeder_combout\,
	ena => \Decoder0~3_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R3(5));

-- Location: LCCOMB_X49_Y3_N12
\R2[5]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \R2[5]~feeder_combout\ = D(5)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => D(5),
	combout => \R2[5]~feeder_combout\);

-- Location: FF_X49_Y3_N13
\R2[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \R2[5]~feeder_combout\,
	ena => \Decoder0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R2(5));

-- Location: FF_X48_Y3_N9
\R0[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	asdata => D(5),
	sload => VCC,
	ena => \Decoder0~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R0(5));

-- Location: LCCOMB_X48_Y3_N6
\R1[5]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \R1[5]~feeder_combout\ = D(5)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => D(5),
	combout => \R1[5]~feeder_combout\);

-- Location: FF_X48_Y3_N7
\R1[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \R1[5]~feeder_combout\,
	ena => \Decoder0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R1(5));

-- Location: LCCOMB_X48_Y3_N8
\Mux2~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux2~0_combout\ = (\RA[0]~input_o\ & ((\RA[1]~input_o\) # ((R1(5))))) # (!\RA[0]~input_o\ & (!\RA[1]~input_o\ & (R0(5))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101010011000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \RA[0]~input_o\,
	datab => \RA[1]~input_o\,
	datac => R0(5),
	datad => R1(5),
	combout => \Mux2~0_combout\);

-- Location: LCCOMB_X45_Y3_N12
\Mux2~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux2~1_combout\ = (\RA[1]~input_o\ & ((\Mux2~0_combout\ & (R3(5))) # (!\Mux2~0_combout\ & ((R2(5)))))) # (!\RA[1]~input_o\ & (((\Mux2~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010111111000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => R3(5),
	datab => R2(5),
	datac => \RA[1]~input_o\,
	datad => \Mux2~0_combout\,
	combout => \Mux2~1_combout\);

-- Location: FF_X45_Y3_N13
\Q[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \Mux2~1_combout\,
	ena => \Q[7]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => Q(5));

-- Location: LCCOMB_X45_Y3_N6
\Mux18~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux18~1_combout\ = (\sel[0]~reg0_q\ & (((PC(1)) # (!\sel[2]~reg0_q\)))) # (!\sel[0]~reg0_q\ & ((Q(5)) # ((\sel[2]~reg0_q\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111000111110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => Q(5),
	datab => \sel[0]~reg0_q\,
	datac => \sel[2]~reg0_q\,
	datad => PC(1),
	combout => \Mux18~1_combout\);

-- Location: LCCOMB_X45_Y3_N8
\Mux18~2\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux18~2_combout\ = (!\sel[1]~reg0_q\ & (\Mux18~0_combout\ & \Mux18~1_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \sel[1]~reg0_q\,
	datac => \Mux18~0_combout\,
	datad => \Mux18~1_combout\,
	combout => \Mux18~2_combout\);

-- Location: FF_X45_Y3_N9
\data[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Mux18~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => data(1));

-- Location: LCCOMB_X51_Y3_N26
\R1[2]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \R1[2]~feeder_combout\ = D(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => D(2),
	combout => \R1[2]~feeder_combout\);

-- Location: FF_X51_Y3_N27
\R1[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \R1[2]~feeder_combout\,
	ena => \Decoder0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R1(2));

-- Location: LCCOMB_X50_Y3_N0
\R3[2]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \R3[2]~feeder_combout\ = D(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => D(2),
	combout => \R3[2]~feeder_combout\);

-- Location: FF_X50_Y3_N1
\R3[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \R3[2]~feeder_combout\,
	ena => \Decoder0~3_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R3(2));

-- Location: FF_X53_Y3_N23
\R0[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	asdata => D(2),
	sload => VCC,
	ena => \Decoder0~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R0(2));

-- Location: LCCOMB_X53_Y3_N0
\R2[2]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \R2[2]~feeder_combout\ = D(2)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => D(2),
	combout => \R2[2]~feeder_combout\);

-- Location: FF_X53_Y3_N1
\R2[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \R2[2]~feeder_combout\,
	ena => \Decoder0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R2(2));

-- Location: LCCOMB_X53_Y3_N22
\Mux5~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux5~0_combout\ = (\RA[1]~input_o\ & ((\RA[0]~input_o\) # ((R2(2))))) # (!\RA[1]~input_o\ & (!\RA[0]~input_o\ & (R0(2))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101010011000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \RA[1]~input_o\,
	datab => \RA[0]~input_o\,
	datac => R0(2),
	datad => R2(2),
	combout => \Mux5~0_combout\);

-- Location: LCCOMB_X44_Y3_N26
\Mux5~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux5~1_combout\ = (\RA[0]~input_o\ & ((\Mux5~0_combout\ & ((R3(2)))) # (!\Mux5~0_combout\ & (R1(2))))) # (!\RA[0]~input_o\ & (((\Mux5~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111010110001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \RA[0]~input_o\,
	datab => R1(2),
	datac => R3(2),
	datad => \Mux5~0_combout\,
	combout => \Mux5~1_combout\);

-- Location: FF_X44_Y3_N27
\Q[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \Mux5~1_combout\,
	ena => \Q[7]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => Q(2));

-- Location: LCCOMB_X49_Y3_N14
\D[6]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \D[6]~feeder_combout\ = \datain[2]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \datain[2]~input_o\,
	combout => \D[6]~feeder_combout\);

-- Location: FF_X49_Y3_N15
\D[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \D[6]~feeder_combout\,
	ena => \en~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => D(6));

-- Location: LCCOMB_X49_Y3_N24
\R2[6]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \R2[6]~feeder_combout\ = D(6)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => D(6),
	combout => \R2[6]~feeder_combout\);

-- Location: FF_X49_Y3_N25
\R2[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \R2[6]~feeder_combout\,
	ena => \Decoder0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R2(6));

-- Location: LCCOMB_X50_Y3_N6
\R3[6]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \R3[6]~feeder_combout\ = D(6)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => D(6),
	combout => \R3[6]~feeder_combout\);

-- Location: FF_X50_Y3_N7
\R3[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \R3[6]~feeder_combout\,
	ena => \Decoder0~3_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R3(6));

-- Location: FF_X48_Y3_N1
\R0[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	asdata => D(6),
	sload => VCC,
	ena => \Decoder0~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R0(6));

-- Location: LCCOMB_X48_Y3_N10
\R1[6]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \R1[6]~feeder_combout\ = D(6)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => D(6),
	combout => \R1[6]~feeder_combout\);

-- Location: FF_X48_Y3_N11
\R1[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \R1[6]~feeder_combout\,
	ena => \Decoder0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R1(6));

-- Location: LCCOMB_X48_Y3_N0
\Mux1~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux1~0_combout\ = (\RA[0]~input_o\ & ((\RA[1]~input_o\) # ((R1(6))))) # (!\RA[0]~input_o\ & (!\RA[1]~input_o\ & (R0(6))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101010011000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \RA[0]~input_o\,
	datab => \RA[1]~input_o\,
	datac => R0(6),
	datad => R1(6),
	combout => \Mux1~0_combout\);

-- Location: LCCOMB_X44_Y3_N12
\Mux1~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux1~1_combout\ = (\RA[1]~input_o\ & ((\Mux1~0_combout\ & ((R3(6)))) # (!\Mux1~0_combout\ & (R2(6))))) # (!\RA[1]~input_o\ & (((\Mux1~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111010110001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \RA[1]~input_o\,
	datab => R2(6),
	datac => R3(6),
	datad => \Mux1~0_combout\,
	combout => \Mux1~1_combout\);

-- Location: FF_X44_Y3_N13
\Q[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \Mux1~1_combout\,
	ena => \Q[7]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => Q(6));

-- Location: LCCOMB_X44_Y3_N14
\Mux17~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux17~0_combout\ = (\sel[0]~reg0_q\ & ((\sel[2]~reg0_q\) # ((Q(2))))) # (!\sel[0]~reg0_q\ & (!\sel[2]~reg0_q\ & ((Q(6)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011100110101000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \sel[0]~reg0_q\,
	datab => \sel[2]~reg0_q\,
	datac => Q(2),
	datad => Q(6),
	combout => \Mux17~0_combout\);

-- Location: LCCOMB_X46_Y3_N24
\Add1~12\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add1~12_combout\ = ((PC(6) $ (\M[0]~input_o\ $ (\Add1~11\)))) # (GND)
-- \Add1~13\ = CARRY((PC(6) & ((!\Add1~11\) # (!\M[0]~input_o\))) # (!PC(6) & (!\M[0]~input_o\ & !\Add1~11\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1001011000101011",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => PC(6),
	datab => \M[0]~input_o\,
	datad => VCC,
	cin => \Add1~11\,
	combout => \Add1~12_combout\,
	cout => \Add1~13\);

-- Location: LCCOMB_X46_Y3_N28
\Mux9~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux9~0_combout\ = (\M[1]~input_o\ & (\Add1~12_combout\ & (!\M[0]~input_o\))) # (!\M[1]~input_o\ & ((\M[0]~input_o\ & (\Add1~12_combout\)) # (!\M[0]~input_o\ & ((D(6))))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100110101001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \M[1]~input_o\,
	datab => \Add1~12_combout\,
	datac => \M[0]~input_o\,
	datad => D(6),
	combout => \Mux9~0_combout\);

-- Location: FF_X46_Y3_N29
\PC[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \Mux9~0_combout\,
	ena => \PC[3]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => PC(6));

-- Location: LCCOMB_X44_Y3_N2
\Mux17~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux17~1_combout\ = (\sel[2]~reg0_q\ & ((\Mux17~0_combout\ & ((PC(2)))) # (!\Mux17~0_combout\ & (PC(6))))) # (!\sel[2]~reg0_q\ & (\Mux17~0_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110110001100100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \sel[2]~reg0_q\,
	datab => \Mux17~0_combout\,
	datac => PC(6),
	datad => PC(2),
	combout => \Mux17~1_combout\);

-- Location: LCCOMB_X44_Y3_N4
\Mux17~2\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux17~2_combout\ = (!\sel[1]~reg0_q\ & \Mux17~1_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \sel[1]~reg0_q\,
	datad => \Mux17~1_combout\,
	combout => \Mux17~2_combout\);

-- Location: FF_X44_Y3_N5
\data[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Mux17~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => data(2));

-- Location: LCCOMB_X46_Y3_N26
\Add1~14\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add1~14_combout\ = \M[0]~input_o\ $ (\Add1~13\ $ (!PC(7)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110011000011",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \M[0]~input_o\,
	datad => PC(7),
	cin => \Add1~13\,
	combout => \Add1~14_combout\);

-- Location: FF_X49_Y3_N31
\D[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \datain[3]~input_o\,
	sload => VCC,
	ena => \en~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => D(7));

-- Location: LCCOMB_X46_Y3_N0
\Mux8~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux8~0_combout\ = (\M[0]~input_o\ & (!\M[1]~input_o\ & (\Add1~14_combout\))) # (!\M[0]~input_o\ & ((\M[1]~input_o\ & (\Add1~14_combout\)) # (!\M[1]~input_o\ & ((D(7))))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111000101100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \M[0]~input_o\,
	datab => \M[1]~input_o\,
	datac => \Add1~14_combout\,
	datad => D(7),
	combout => \Mux8~0_combout\);

-- Location: FF_X46_Y3_N1
\PC[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \Mux8~0_combout\,
	ena => \PC[3]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => PC(7));

-- Location: LCCOMB_X49_Y3_N0
\R2[7]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \R2[7]~feeder_combout\ = D(7)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => D(7),
	combout => \R2[7]~feeder_combout\);

-- Location: FF_X49_Y3_N1
\R2[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \R2[7]~feeder_combout\,
	ena => \Decoder0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R2(7));

-- Location: LCCOMB_X50_Y3_N14
\R3[7]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \R3[7]~feeder_combout\ = D(7)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => D(7),
	combout => \R3[7]~feeder_combout\);

-- Location: FF_X50_Y3_N15
\R3[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \R3[7]~feeder_combout\,
	ena => \Decoder0~3_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R3(7));

-- Location: FF_X48_Y3_N25
\R0[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	asdata => D(7),
	sload => VCC,
	ena => \Decoder0~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R0(7));

-- Location: LCCOMB_X48_Y3_N18
\R1[7]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \R1[7]~feeder_combout\ = D(7)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => D(7),
	combout => \R1[7]~feeder_combout\);

-- Location: FF_X48_Y3_N19
\R1[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \R1[7]~feeder_combout\,
	ena => \Decoder0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R1(7));

-- Location: LCCOMB_X48_Y3_N24
\Mux0~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux0~0_combout\ = (\RA[0]~input_o\ & ((\RA[1]~input_o\) # ((R1(7))))) # (!\RA[0]~input_o\ & (!\RA[1]~input_o\ & (R0(7))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011101010011000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \RA[0]~input_o\,
	datab => \RA[1]~input_o\,
	datac => R0(7),
	datad => R1(7),
	combout => \Mux0~0_combout\);

-- Location: LCCOMB_X45_Y3_N14
\Mux0~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux0~1_combout\ = (\RA[1]~input_o\ & ((\Mux0~0_combout\ & ((R3(7)))) # (!\Mux0~0_combout\ & (R2(7))))) # (!\RA[1]~input_o\ & (((\Mux0~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111010110001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \RA[1]~input_o\,
	datab => R2(7),
	datac => R3(7),
	datad => \Mux0~0_combout\,
	combout => \Mux0~1_combout\);

-- Location: FF_X45_Y3_N15
\Q[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \Mux0~1_combout\,
	ena => \Q[7]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => Q(7));

-- Location: LCCOMB_X50_Y3_N16
\R3[3]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \R3[3]~feeder_combout\ = D(3)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => D(3),
	combout => \R3[3]~feeder_combout\);

-- Location: FF_X50_Y3_N17
\R3[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \R3[3]~feeder_combout\,
	ena => \Decoder0~3_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R3(3));

-- Location: LCCOMB_X51_Y3_N30
\R1[3]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \R1[3]~feeder_combout\ = D(3)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => D(3),
	combout => \R1[3]~feeder_combout\);

-- Location: FF_X51_Y3_N31
\R1[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \R1[3]~feeder_combout\,
	ena => \Decoder0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R1(3));

-- Location: FF_X52_Y3_N23
\R0[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	asdata => D(3),
	sload => VCC,
	ena => \Decoder0~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R0(3));

-- Location: LCCOMB_X52_Y3_N28
\R2[3]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \R2[3]~feeder_combout\ = D(3)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => D(3),
	combout => \R2[3]~feeder_combout\);

-- Location: FF_X52_Y3_N29
\R2[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \R2[3]~feeder_combout\,
	ena => \Decoder0~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => R2(3));

-- Location: LCCOMB_X52_Y3_N22
\Mux4~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux4~0_combout\ = (\RA[0]~input_o\ & (\RA[1]~input_o\)) # (!\RA[0]~input_o\ & ((\RA[1]~input_o\ & ((R2(3)))) # (!\RA[1]~input_o\ & (R0(3)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101110010011000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \RA[0]~input_o\,
	datab => \RA[1]~input_o\,
	datac => R0(3),
	datad => R2(3),
	combout => \Mux4~0_combout\);

-- Location: LCCOMB_X45_Y3_N24
\Mux4~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux4~1_combout\ = (\RA[0]~input_o\ & ((\Mux4~0_combout\ & (R3(3))) # (!\Mux4~0_combout\ & ((R1(3)))))) # (!\RA[0]~input_o\ & (((\Mux4~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010111111000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => R3(3),
	datab => R1(3),
	datac => \RA[0]~input_o\,
	datad => \Mux4~0_combout\,
	combout => \Mux4~1_combout\);

-- Location: FF_X45_Y3_N25
\Q[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div_clk~clkctrl_outclk\,
	d => \Mux4~1_combout\,
	ena => \Q[7]~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => Q(3));

-- Location: LCCOMB_X45_Y3_N28
\Mux16~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux16~0_combout\ = (\sel[2]~reg0_q\ & (\sel[0]~reg0_q\)) # (!\sel[2]~reg0_q\ & ((\sel[0]~reg0_q\ & ((Q(3)))) # (!\sel[0]~reg0_q\ & (Q(7)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101110010011000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \sel[2]~reg0_q\,
	datab => \sel[0]~reg0_q\,
	datac => Q(7),
	datad => Q(3),
	combout => \Mux16~0_combout\);

-- Location: LCCOMB_X45_Y3_N18
\Mux16~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux16~1_combout\ = (\sel[2]~reg0_q\ & ((\Mux16~0_combout\ & ((PC(3)))) # (!\Mux16~0_combout\ & (PC(7))))) # (!\sel[2]~reg0_q\ & (((\Mux16~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111010110001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \sel[2]~reg0_q\,
	datab => PC(7),
	datac => PC(3),
	datad => \Mux16~0_combout\,
	combout => \Mux16~1_combout\);

-- Location: LCCOMB_X45_Y3_N30
\Mux16~2\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Mux16~2_combout\ = (!\sel[1]~reg0_q\ & \Mux16~1_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \sel[1]~reg0_q\,
	datad => \Mux16~1_combout\,
	combout => \Mux16~2_combout\);

-- Location: FF_X45_Y3_N31
\data[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Mux16~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => data(3));

-- Location: LCCOMB_X45_Y3_N20
\WideOr6~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \WideOr6~0_combout\ = (data(2) & ((data(1)) # (data(0) $ (data(3))))) # (!data(2) & ((data(1) $ (data(3))) # (!data(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101011111101101",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => data(0),
	datab => data(1),
	datac => data(2),
	datad => data(3),
	combout => \WideOr6~0_combout\);

-- Location: FF_X45_Y3_N21
\seg[0]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \WideOr6~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \seg[0]~reg0_q\);

-- Location: LCCOMB_X43_Y3_N16
\WideOr5~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \WideOr5~0_combout\ = (data(3) & ((data(0) & ((!data(1)))) # (!data(0) & (!data(2))))) # (!data(3) & ((data(1) $ (!data(0))) # (!data(2))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110101010111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => data(2),
	datab => data(3),
	datac => data(1),
	datad => data(0),
	combout => \WideOr5~0_combout\);

-- Location: FF_X43_Y3_N17
\seg[1]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \WideOr5~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \seg[1]~reg0_q\);

-- Location: LCCOMB_X43_Y3_N30
\WideOr4~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \WideOr4~0_combout\ = (data(2) & (((!data(1) & data(0))) # (!data(3)))) # (!data(2) & ((data(3)) # ((data(0)) # (!data(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111111101100111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => data(2),
	datab => data(3),
	datac => data(1),
	datad => data(0),
	combout => \WideOr4~0_combout\);

-- Location: FF_X43_Y3_N31
\seg[2]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \WideOr4~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \seg[2]~reg0_q\);

-- Location: LCCOMB_X43_Y3_N12
\WideOr3~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \WideOr3~0_combout\ = (data(1) & ((data(2) & ((!data(0)))) # (!data(2) & ((data(0)) # (!data(3)))))) # (!data(1) & ((data(3)) # (data(2) $ (!data(0)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101111010111101",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => data(2),
	datab => data(3),
	datac => data(1),
	datad => data(0),
	combout => \WideOr3~0_combout\);

-- Location: FF_X43_Y3_N13
\seg[3]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \WideOr3~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \seg[3]~reg0_q\);

-- Location: LCCOMB_X43_Y3_N10
\WideOr2~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \WideOr2~0_combout\ = (data(1) & (((data(3)) # (!data(0))))) # (!data(1) & ((data(2) & (data(3))) # (!data(2) & ((!data(0))))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100100011111101",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => data(2),
	datab => data(3),
	datac => data(1),
	datad => data(0),
	combout => \WideOr2~0_combout\);

-- Location: FF_X43_Y3_N11
\seg[4]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \WideOr2~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \seg[4]~reg0_q\);

-- Location: LCCOMB_X44_Y3_N10
\WideOr1~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \WideOr1~0_combout\ = (data(2) & ((data(1) $ (!data(3))) # (!data(0)))) # (!data(2) & ((data(3)) # ((!data(1) & !data(0)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101001011111011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => data(2),
	datab => data(1),
	datac => data(3),
	datad => data(0),
	combout => \WideOr1~0_combout\);

-- Location: FF_X44_Y3_N11
\seg[5]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \WideOr1~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \seg[5]~reg0_q\);

-- Location: LCCOMB_X43_Y3_N28
\WideOr0~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \WideOr0~0_combout\ = (data(0) & ((data(3)) # (data(2) $ (data(1))))) # (!data(0) & ((data(1)) # (data(2) $ (data(3)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1101111011110110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => data(2),
	datab => data(3),
	datac => data(1),
	datad => data(0),
	combout => \WideOr0~0_combout\);

-- Location: FF_X43_Y3_N29
\seg[6]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \WideOr0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \seg[6]~reg0_q\);

ww_sel(0) <= \sel[0]~output_o\;

ww_sel(1) <= \sel[1]~output_o\;

ww_sel(2) <= \sel[2]~output_o\;

ww_seg(0) <= \seg[0]~output_o\;

ww_seg(1) <= \seg[1]~output_o\;

ww_seg(2) <= \seg[2]~output_o\;

ww_seg(3) <= \seg[3]~output_o\;

ww_seg(4) <= \seg[4]~output_o\;

ww_seg(5) <= \seg[5]~output_o\;

ww_seg(6) <= \seg[6]~output_o\;

ww_seg(7) <= \seg[7]~output_o\;
END structure;


